Abstract:
Charge pump circuits is a type of DC-DC converter in which different DC level can be obtained from constant DC input level. Usually, CP circuit are designed to be realized as integrated circuit form. One of the most important factors that affect the operation of analog IC is the parasitic capacitance associated with transistors and capacitors where it is effect is at high frequencies on the output voltage as well as the efficiency because it drains a portion of the charge being transferred and thus negatively affects the performance of the electronic circuits. This paper presents a comparative study between four different CP realizations in terms of its sensitivity to parasitic capacitances associated with pumping capacitorsand note which of these topologies is more affected by parasitic capacitors since the aim of CP implementation is the integrated realization of these circuits. This paper includes a comparison between mathematical analysis and simulation using Advanced Design System (ADS) simulation software to evaluate the performance of these circuits.
Keywords: Charge pumps, Dickson CP, Cockcroft-Walton CP, Pelliconi CP, Bootstrap CP.
REFERENCES
Abaravicius, B., Cochran, S. and Mitra, S., 2021. High-efficiency high voltage hybrid charge pump design with an improved chip area. IEEE Access, 9, pp.94386-94397.
Allasasmeh, Y. and Gregori, S., 2009, August. A performance comparison of Dickson and Fibonacci charge pumps. In 2009 European Conference on Circuit Theory and Design (pp. 599-602). IEEE.
Allasasmeh, Y. and Gregori, S., 2010, August. Charge reusing in switched-capacitor voltage multipliers with reduced dynamic losses. In 2010 53rd IEEE International Midwest Symposium on Circuits and Systems (pp. 1169-1172). IEEE.
Atsumi, S., Kuriyama, M., Umezawa, A., Banba, H., Naruke, K., Yamada, S., Ohshima, Y., Oshikiri, M., Hiura, Y., Yamane, T. and Yoshikawa, K., 1994. A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation. IEICE Transactions on Electronics, 77(5), pp.791-799.
Bi, H., 2023. Design of a high voltage charge pump in advanced.
Cockcroft, J.D. and Walton, E.T., 1932. Experiments with high velocity positive ions.―(I) Further developments in the method of obtaining high velocity positive ions. Proceedings of the royal society of London. Series A, containing papers of a mathematical and physical character, 136(830), pp.619-630.
Dickson, J.F., 1976. On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique. IEEE Journal of solid-state circuits, 11(3), pp.374-378.
Ho, T.S., Ramiah, H., Churchill, K.K.P., Chen, Y., Lim, C.C., Lai, N.S., Mak, P.I. and Martins, R.P., 2022. Low voltage switched-capacitive-based reconfigurable charge pumps for energy harvesting systems: An overview. IEEE Access, 10, pp.126910-126930.
Hsu, C.P. and Lin, H., 2010. Analytical models of output voltages and power efficiencies for multistage charge pumps. IEEE Transactions on Power Electronics, 25(6), pp.1375-1385.
Jinbo, T., Nakata, H., Hashimoto, K., Watanabe, T., Ninomiya, K., Urai, T., Koike, M., Sato, T., Kodama, N., Oyama, K.I. and Okazawa, T., 1992. A 5-V-only 16-Mb flash memory with sector erase mode. IEEE journal of solid-state circuits, 27(11), pp.1547-1554.
Ker, M.D., Chen, S.L. and Tsai, C.S., 2006. Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes. IEEE Journal of solid-state circuits, 41(5), pp.1100-1107.
Navidi, M.M. and Graham, D.W., 2017, May. A regulated charge pump for injecting floating-gate transistors. In 2017 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1-4). IEEE.
Palumbo, G. and Pappalardo, D., 2010. Charge pump circuits: An overview on design strategies and topologies. IEEE Circuits and Systems Magazine, 10(1), pp.31-45.
Palumbo, G., Pappalardo, D. and Gaibotti, M., 2006. Charge pump with adaptive stages for non-volatile memories. IEE Proceedings-Circuits, Devices and Systems, 153(2), pp.136-142.
Pelliconi, R., Iezzi, D., Baroni, A., Pasotti, M. and Rolandi, P.L., 2001, September. Power efficient charge pump in deep submicron standard CMOS technology. In Proceedings of the 27th European Solid-State Circuits Conference (pp. 73-76). IEEE.
Pulvirenti, F., 2022. 3-V Input, 70-V Output, Fully Integrated Hybrid Charge Pump. IEEE Access, 10, pp.44062-44075.
Shen, B., Bose, S. and Johnston, M.L., 2018. A 1.2 V–20 V closed-loop charge pump for high dynamic range photodetector array biasing. IEEE Transactions on Circuits and Systems II: Express Briefs, 66(3), pp.327-331.
Song, M. and Ikehashi, T., 2024. A Capacitance Varying Charge Pump with Exponential Stage-Number Dependence and Its Implementation by MEMS Technology. IEICE Transactions on Electronics, 107(1), pp.1-11.
Tanzawa, T. and Tanaka, T., 1997. A dynamic analysis of the Dickson charge pump circuit. IEEE Journal of solid-state circuits, 32(8), pp.1231-1240.
Toft, J.K. and Jorgensen, I.H., 2021. A 5 V to 180 V Charge Pump for Capacitive Loads in a 180 nm SOI Process. Elektronika ir Elektrotechnika, 27(6), pp.35-41.
Umezawa, A., Atsumi, S., Kuriyama, M., Banba, H., Imamiya, K.I., Naruke, K., Yamada, S., Obi, E., Oshikiri, M., Suzuki, T. and Tanaka, S., 1992. A 5-V-only operation 0.6-mu m flash EEPROM with row decoder scheme in triple-well structure. IEEE Journal of Solid-State Circuits, 27(11), pp.1540-1546.
Weiner, M.M., 1969. Analysis of Cockcroft‐Walton Voltage Multipliers with an Arbitrary Number of Stages. Review of Scientific Instruments, 40(2), pp.330-333.