JMCER

Modified Absolute Sinusoidal PWM Control of a Self-Balanced 17- Level Switched-Capacitor Inverter with Asymmetric Capacitor Voltages

  • Received
    August 20, 2026
  • Revised
    September 21, 2026
  • Accepted
    October 1, 2026
  • Published
    October 3, 2026

Authors

  • Saqarharb Mohammed
  • Rakan Khalil Antar

Abstract

A 17-level switched-capacitor inverter is presented in which four capacitors are held at two different voltages, two at the input voltage and two at half of it, so that the smallest voltage step the converter can synthesise is 23.59 V from a 47.175 V source. The structure delivers seventeen levels and a fourfold voltage gain from fourteen switches, four capacitors, two diodes and one DC source, twenty main power components in all, which gives a component-to-level ratio of 1.18 and a cost function of 2.38. Balancing is inherent, so no voltage sensor, no balancing controller and no redundant-state selection are required. The converter is driven by modified absolute sinusoidal PWM, whose eight switching angles are computed before the converter runs, so each device commutates twice per fundamental cycle rather than the 200 times a 10 kHz carrier would demand, and the switching loss is held to 0.07 W of a 1.88 W total. Simulation returns a fundamental of 187.7 V, an output of 132.7 V rms and a voltage distortion of 2.53%. An FPGA-controlled prototype supplying a 180 W single-phase induction motor at a power factor of 0.76 returned 186.7 V, 132.3 V rms, a gain of 3.96 against the ideal 4.00, a measured voltage distortion of 2.9%, a measured current distortion of 2.8% and an efficiency of 94.6%, with capacitor ripples between 2.3% and 4.5% and no device stressed above 143.3 V. The total standing voltage is 1073.6 V, that is 5.69 per unit.


Keywords: MASPWM, Switched-capacitor inverter, Multilevel inverter, Self-balancing, Total harmonic distortion.


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